1. Field of the Invention
The present invention relates to an improvement in a plurality of ECL (emitter-coupled logic) output buffer circuits connected in parallel with each other to one bus.
2. Description of the Related Art
FIG. 1 shows a conventional bus structure.
In this bus structure, a plurality of ECL output buffer circuits 1A to 1C and one or more ECL input buffer circuits 2 are connected in parallel with each other to one bus.
In the ECL output buffer circuits 1A to 1C, reference numeral 3 denotes a differential switch constituting an ECL output buffer circuit main portion; and 4, an emitter follower.
The base of an npn bipolar transistor 5 is connected to an input terminal IN. The base of an npn bipolar transistor 6 is connected to a terminal 24. A reference potential Vref is applied to the terminal 24. The emitters of both the transistors 5 and 6 are connected to a power-supply terminal 12 via a constant-current source 7. For example, a potential of -4.5 V is applied to the power-supply terminal 12.
The collector of the transistor 5 is connected to a power-supply terminal 13. For example, a ground potential (0 V) is applied to the power-supply terminal 13. The collector of the transistor 6 is connected to the power-supply terminal 13 via a resistor 8. The base of an npn bipolar transistor 9 constituting the emitter follower 4 is connected to the collector of the transistor 6. The collector of the transistor 9 is connected to the power-supply terminal 13. The emitter of the transistor 9 is connected to a bus BUS.
The bus BUS is connected to a terminating power-supply terminal 11 via a load resistor (e.g., 50 .OMEGA.) 10. For example, a potential of -2 V is applied to the terminating power-supply terminal 11.
In the ECL input buffer circuit 2, reference numeral 18 denotes an npn bipolar transistor; 19, a resistor; and 20, a differential switch.
The base of an npn bipolar transistor 14 is connected to the bus BUS. The base of an npn bipolar transistor 15 is connected to a terminal 25. The reference potential Vref is applied to the terminal 25. The emitters of both the transistors 14 and 15 are connected to a power-supply terminal 26 via a constant-current source 16. For example, a potential of -4.5 V is applied to the power-supply terminal 26.
The collector of the transistor 14 is connected to a power-supply terminal 27. For example, a ground potential (0 V) is applied to the power-supply terminal 27. The collector of the transistor 15 is connected to the power-supply terminal 27 via a resistor 17. The base of the bipolar transistor 18 constituting an emitter follower is connected to the collector of the transistor 15. The collector of the transistor 18 is connected to the power-supply terminal 27. The emitter of the transistor 18 is connected to the power-supply terminal 26 via the resistor 19.
In the above-described bus structure, the output portions of the ECL output buffer circuits 1A to 1C respectively constitute emitter followers. That is, the bus structure is a wired-OR structure. Note that in the wired-OR structure, when at least one of output signals from the plurality of ECL output buffer circuits connected in parallel with each other to the bus BUS is set at "H (high)" level, the bus BUS is set at "H" level.
When, therefore, a signal is to be exchanged between one ECL output buffer circuit and one ECL input buffer circuit, output signals from the remaining ECL output buffer circuits connected to the bus BUS may be set at "L (low)" level.
Assume that in FIG. 1, the ECL output buffer circuit 1C is to transmit a signal, and the ECL input buffer circuit 2 is to receive the signal. In this case, when output signals from the ECL output buffer circuits 1A and 1B are set at "L" level to set the circuits in a standby state, the output signal ("H" or "L" level) from the ECL output buffer circuit 1C is transmitted to the ECL input buffer circuit 2 via the bus BUS.
In the above-described bus structure, however, currents flow not only from the ECL output buffer circuit which is to transmit a signal but also from the ECL output buffer circuits in a standby state, which are to transmit no signals, to the terminating power-supply terminal 11 via the load resistor 10.
For this reason, as the number of ECL output buffer circuits connected to the bus BUS increases, a current flowing from the ECL output buffer circuit, which is to transmit a signal, to the load resistor 10 decreases, and a base-emitter voltage VBE of the bipolar transistor (emitter follower) of the ECL output buffer circuit which is to transmit the signal decreases. As a result, the "L"-level signal output from the ECL output buffer circuit to the bus BUS is increased in signal level.
This increase in signal level reduces the margin of "L" level detection of the ECL input buffer circuit. In addition, since the "L" level detection margin of the ECL input buffer circuit is generally as low as about 0.8 V, an erroneous operation of the ECL input buffer circuit tends to occur.
That is, in order to prevent an erroneous operation of the ECL input buffer circuit, the number of ECL output buffer circuits connected to the bus cannot be increased.